JPS6322396B2 - - Google Patents
Info
- Publication number
- JPS6322396B2 JPS6322396B2 JP58169891A JP16989183A JPS6322396B2 JP S6322396 B2 JPS6322396 B2 JP S6322396B2 JP 58169891 A JP58169891 A JP 58169891A JP 16989183 A JP16989183 A JP 16989183A JP S6322396 B2 JPS6322396 B2 JP S6322396B2
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- address
- power supply
- gate
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58169891A JPS6061996A (ja) | 1983-09-14 | 1983-09-14 | 不揮発性メモリのアドレスデコ−ダ回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58169891A JPS6061996A (ja) | 1983-09-14 | 1983-09-14 | 不揮発性メモリのアドレスデコ−ダ回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6061996A JPS6061996A (ja) | 1985-04-09 |
JPS6322396B2 true JPS6322396B2 (en]) | 1988-05-11 |
Family
ID=15894873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58169891A Granted JPS6061996A (ja) | 1983-09-14 | 1983-09-14 | 不揮発性メモリのアドレスデコ−ダ回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6061996A (en]) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5051959A (en) * | 1985-08-14 | 1991-09-24 | Fujitsu Limited | Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type |
JP2722536B2 (ja) * | 1988-10-15 | 1998-03-04 | ソニー株式会社 | 不揮発性メモリのアドレスデコーダ回路 |
JPH0821849B2 (ja) * | 1988-10-25 | 1996-03-04 | 富士通株式会社 | 半導体記憶装置 |
JPH0793026B2 (ja) * | 1989-09-20 | 1995-10-09 | 富士通株式会社 | デコーダ回路 |
JPH0684354A (ja) * | 1992-05-26 | 1994-03-25 | Nec Corp | 行デコーダ回路 |
JPH08227596A (ja) * | 1994-11-30 | 1996-09-03 | Texas Instr Inc <Ti> | 半導体メモリ用デコード回路 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5913117B2 (ja) * | 1980-05-19 | 1984-03-27 | 株式会社東芝 | 半導体メモリ |
-
1983
- 1983-09-14 JP JP58169891A patent/JPS6061996A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6061996A (ja) | 1985-04-09 |
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